A chip generally outputs a signal generated thereby or receives a signal from an external circuit via an input/output port circuit disposed therein. Sometimes, electrostatic discharge (ESD) generated by the external circuit coupled to the chip may enter the chip via the I/O circuit as well. The electrostatic discharge may undesirably damage the chip or adversely affect the function of the chip.
Please refer to FIG. 1 which schematically illustrates an I/O circuit with ESD protecting means. As shown, an I/O circuit 10 is disposed in a chip 12 and coupled to an external circuit 14 and a driving voltage VPP. The I/O circuit 10 is an open drain I/O including a pull-down circuit 16 and a P-type transistor Mp for ESD protection. The source, gate and body of the P-type transistor Mp are electrically connected to the driving voltage VPP, and the drain is electrically connected to the pull-down circuit 16, an internal circuit 11 inside the chip 12 and the external circuit 14 via the node Nout.
Through the P-type transistor Mp, a current path can be formed between the driving voltage VPP and the external circuit 14. Therefore, the electrostatic current generated by the external circuit 14 can be bypassed to the driving voltage VPP via the current path and the chip 12 is protected from possible damage. On the other hand, for avoiding the effect of the P-type transistor Mp and/or the driving voltage VPP on the principal function of chip 12, the P-type transistor Mp should be always turned off. This object can be achieved by the architecture of FIG. 1 wherein the source and gate electrodes of the P-type transistor Mp is commonly coupled to the driving voltage VPP.